High-speed shortest path co-processor design

Abstract

Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read input, compute the result and set the output which later on will slow down the overall performance. Therefore, this research proposed a hardware approach which implemented Field Programmable Gate Array (FPGA) technology to find the shortest path between two nodes by using A-Star algorithm. The main contributions of this research consisted of the analysis of single and parallel architecture and the implementation in FPGA that gave the suitable route to find the shortest route with less time used. A-star algorithm was chosen for the shortest path calculation since it could achieve superior time running based on its heuristic behavior. The algorithm always searched for the best node based on a cost function and the ability to find a path with minimal cost, if it existed. This thesis also presented methods, architecture and results of the high-speed shortest path coprocessor. Furthermore, the FPGA approach demonstrated that the results and performance of hardware implementation could reduce calculation time compared to software implementation.